On Distributed Communications Series

VII. Tentative Engineering Specifications and Preliminary Design for a High-Data-Rate Distributed Network Switching Node

Part Two: Implementation Proposal

I. Detailed Flow Charts

The following block diagrams and flow charts describe the Central Processor, the Link Units, and the Buffers. The logical design was taken only to the point necessary to determine the major equipment elements needed to perform all the known key functions within the circuitry-timing constraint. No attempt has been made to define a final system configuration.

Intuitively, it is felt that there is enough "fat" in the layout to counterbalance the parts inadvertently omitted.

Separate flow diagrams (Figs. 2-5) are included for the Central Processor, the Input Link Unit, the Output Link Unit, and the Input and Output Buffers (both on a single sheet).

The abbreviation F/F stands for "equivalent flip-flops," which is a unit of circuit complexity corresponding to the number of components required by a single flip-flop stage, together with a modicum of input gating logic.

Most of the Switching Node is to be built of flip-flops connected in a highly iterative register-type structure. Certain of the registers of the Central Processor will require a very heavy logical gating. However, the use of a "standard" flip-flop, for purposes of determining the part-count, appears justified by the heavy counterbalancing number of lightly gated units found in the eight Input, Output, and Buffer Units. The clock speed of the Input, Output, and Buffer Units must be that of the incoming bit rate: 1,540,000 bits/sec. However, a sizable portion of the Central Processor operates most economically at a much higher speed. A 10-megabit/sec capability is used within the Working Registers. A transfer into storage can be performed by present-day l-

On the left side of Fig. 2 is a bank of flip-flop registers which monitor the activities of each of the eight separate Link Units. These provide the intercommunication capability between the Central processor and the Link Units. Other registers indicate the points of program interruption and permit the Central Processor to hop from Link Unit to Link Unit, depending on which requires attention, in the style of a conventional multi-sequence processor.

Three 32-bit registers intercommunicate between a common high-speed core storage unit and the Link Units. A 32-bit portion of a Message Block is transferred to a Working Register. Once in the Working Register, the input word is read into core storage at a location determined by the Line Number (three bits), plus Carbon Copy Number (next two bits), plus Message Block word number (next five bits). Although it does not seem required, an Index Register has been included.

A "read-only, plug-in type wired logic provides program memory.

The Input Link Unit first restrobes the input pulse train. Next, it strips every sixteenth bit, which the Output Link Unit inserted to avoid the need for DC coupling on the transmission links. Next, error detection is per-formed by a shift register and the output stream is logically added to a cryptographic stream generator to produce a clean text output. Clocking means are included to permit automatic resynchronization of the input wave train.

The Input Buffer Unit performs a serial-to-parallel conversion of the input binary stream; the Output Buffer performs a parallel-to-serial conversion.

The Output Link Unit is almost a mirror image of the Input Unit and performs the encrypting, error detection, symbol addition, and every-sixteenth-bit blanking operation.

Part One: General Specifications
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