On Distributed Communications Series

VII. Tentative Engineering Specifications and Preliminary Design for a High-Data-Rate Distributed Network Switching Node

II. Central Processor Description

The key operations that must be performed by the Switching Node are presented in Table I. No attempt will be made to describe the operation of the Central Processor in any greater detail.

The priority order of the operations, the number of bits allocated for specific purposes, and the purpose of the key registers are presented in tabular form in the following subsections. These, together with the flow charts, delineate the operations that are carried out in the Link Units, Buffer, and Central Processor.

The flow charts (Figs. 6-8, 10) are a combination representation of wired-in, highly parallel, logical state testing, and serial steps of the conventional type general-purpose computer operations. An asterisk denotes where general-purpose computer type commands requiring core storage are implied. The remaining blocks are wired-in tests performed rapidly and continuously.

The subroutines that are most critical in timing requirements have been flow-charted in some detail, while those operations which occur less often and which are not too complex have not been detailed.

Programming Priority Rules

This section establishes the order in which the various subroutines within the Central Processor are handled. As the unloading of Input Buffers and the loading of Output Buffers cannot be delayed while a multi-step arithmetic subroutine is being processed, without incurring the possibility of a traffic overload, a special-treatment processing-procedure grade is defined:

Priority I: Input-Buffer-to-Storage Subroutine (IBTS).[1]
Output-Buffer-to- Storage Subroutine (OBTS).
Lower-priority subroutines are processed only when there are no Priority I requirements awaiting action:

Priority II: Decide-Best-Route Subroutine (DBR).
No-Error-Verification Subroutine (NEV).
Choke-Input Subroutine (CI).
Because of Priority-I interrupts, all Priority-II subroutines should be written so that they can be interrupted at any point and restarted without having to back up.

Priority III: Update-Handover-Nuznber-Table Subroutine (UHNT).
Priority IV: Transmit-Trouble-Message Subroutine (TTM).
Priority V: Wait-and-Twiddle-Thumbs Subroutine (/TT)

Intra-Switching Node Message Block Housekeeping bits

Table II denotes the number of bits reserved within each Message Block for each of the specified functions.

If every sixteenth bit is a dummy bit reserved for inserting polarity change to simplify transmission-link requirements, then the percentage of active information flow drops; i.e.,

Common Flag Registers

The Common Flag Registers form part of the Central Processor and are used in the determination of program interrupts and selection of the next program stop (see Table III).

Line State Registers

The Line State Registers (one for each line) form part of the Central Processor and allow the Central Processor to monitor the status of all input and output links to determine which units are in need of attention (see Table IV).

Working Registers

The Working Registers form the heart of the Central Processor. All communications into and out of the core are via these registers. All arithmetic operations are carried out by these registers serving as arithmetic units (see Table V).

Learning and Forgetting Function

The Central Processor via the Update Handover Number Subroutine (Fig. 8) executes the following equations:

where:

 k1    = Learning c onstant;[2]

This manipulation permits the Switching Node to modify its Handover Number Table in response to external changes in the network status, as shown in Fig. 9.

In order to reduce the time taken by the multiplication operation in the handover number modification, the values of the multipliers k1 and k2 are limited to binary numbers containing but two "ones." This permits the use of a specially designed high-speed multiplier that need not anticipate encountering many iterative additions.

Table VI lists the 13 valid values of k1 and k2 out of the 16 combinations of four binary digits which meet the criterion of no more than two "ones" in any number.


[1] Initials are used to denote subroutines and operation registers.

[2] See ODC-II and -III for a detailed description of learning.


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