On Distributed Communications Series
VII. Tentative Engineering Specifications and Preliminary Design for a High-Data-Rate Distributed Network Switching Node
Because of the highly iterative structure of the circuitry used in the Switching Node, the designer must avoid buildup of cumulative time delays which would require extremely fast and expensive circuitry. A slight rearrangement of the organization of circuit elements within the system can cut down propagation delays to permit maximum use of the proposed low-cost transistors.
For example, in Fig. 16, two different methods of performing the division operation of a Message Block by a fixed Boolean polynomial as required in the error detection encoder and decoder circuits are shown. The two methods are highly logically similar; the second circuit requires four serial gates, and so should be avoided in preference to the first circuit.
Fig. 16--Two Circuits for Dividing by 1 +X3+X4+X5+X6
Parts Count Calculations
The total number of equivalent flip-flop stages 3600, as shown in Table VIII. The number of transistors, in all circuits,
The component failure rate for all non-transistorized elements combined is assumed to have a gross failure rate roughly equal to that of the transistorized pieces.
Assumed Failure Rate Calculation
It is assumed that the equipment will operate 24 hr/ day, and will be housed in a foam-insulated box, air conditioned by a closed-cycle refrigeration system normally operating at 15C. The system will also be capable of operating for extended periods at 30C, and, under battle-short conditions for short periods, at 50C using blowers only.
Low-cost germanium transistors of well known life characteristics will be used. Experience of the Computer Sciences Department at RAND over a six-month period with a home-built experimental system, using 10,000 one-dollar transistors, indicates that a failure rate lower than 0.02 per cent per 1000 hr is achievable.
Fifty per cent of the failures are assumed to be dealt with during routine maintenance (once per month). The remainder will be unexpected failures. This gives a catastrophic-failure rate of 0.01 per cent for transistors alone.
Following are the calculations for the mean time between failures (MTBF) for transistors:
MTBF for a single particular link is:
MTBF for the Central Processor plus Core is:
Any failure anywhere within a Node, including those minor failures which permit the Node to continue operating but with one or more of its Link Units down, is summarized as follows:
The use of new, low-cost silicon transistors would eliminate the need for refrigeration and, perhaps, increase the MTBF.
If there is a failure of the Central Processor or the Core Power Supply, either of which will take down the entire Switching Node, a repairman will be dispatched from the nearest Multiplexing Station. An average one-way travel time of five hours is assumed from time of alarm.
If the trouble is in any one of the eight Link Units or Buffers, which would disable only the one Link, the repair may be deferred until it is necessary to change the key during the routine maintenance period. A once-permonth marginal check coincident with a key change will constitute the routine maintenance.
Heat and Power CalculationsHeat and power requirements are summarized as follows:
7) U = 0.2 assuming 1" rigid insulation. 
12) Theoretical equivalent of 1 ton of air conditioning = 0876 hp.
 Peterson, W. Wesley, Error Correcting Codes, Wiley, 1961, pp. 111, 130.