A Technique for Improving Wireability in Automated Circuit Card Place- ments.
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Documentation of an algorithm for automatically placing electronic components on printed circuit cards so as to minimize wiring congestion. Previous methods have sought to position the components to minimize the total wire length, whereas the new method considers only the anticipated degree of congestion in deciding between two trial placements. Implementation of a simplified version at IBM General Products Division resulted in a "surprising" reduction in the number of unwired nets. The technique was developed assuming use of the associated routing program, which attempts to route all nets via minimal paths before resorting to a maze-running approach. 16 pp. Refs. (MW)
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